Understanding the Memory Bus Width of Nvidia's Series 40 Cards

The Nvidia series 40 cards have sparked a lot of interest and discussion among gamers and tech enthusiasts. One aspect that has raised eyebrows is the lower memory bus width compared to previous generations. In this documentation, we will delve into the reasons behind this design choice and explore its implications on performance.

Memory bus width is an important factor in determining the memory bandwidth of a graphics card. A higher memory bus width generally translates to higher memory bandwidth, which is crucial for high-performance graphics rendering. However, the series 40 cards, such as the 4060 Ti, have a lower memory bus width compared to their predecessors.

Fewer but Larger Memory Chips

As explained by BmanUltima, the 4060 Ti has four 2GB chips with 32-bit addressing each, whereas the 1060 6GB has six 1GB chips with 32-bit addressing each. This design change has resulted in a lower memory bus width. However, it's essential to note that the memory transfer frequency of GDDR6 is higher than that of GDDR5, which contributes to increased memory bandwidth.

Impact of L2 Cache on Performance

nezeta highlights the significant role of L2 cache in the series 40 cards. The 4060 Ti boasts a massive 32MB of L2 cache, which will vastly increase the effective bandwidth, particularly at lower resolutions. This is similar to AMD's RX 7600, which has 32MB of L3 cache, adding up to 476.9 GB/s of memory bandwidth.

Performance vs. Specifications

Qazax1337 emphasizes that memory bus bandwidth does not directly translate into performance, especially across different generations. The required performance can be met without needing a wider bus width, thanks to improvements in the GPU die. This is analogous to how a new quad-core CPU can outperform an older hexacore CPU due to IPC improvements.

Comparison with Previous Generations

Even-Run-5274 points out that the 3060 Ti has a 256-bit bus width and 448 GB/s bandwidth, almost twice that of the 4060 Ti. However, it's essential to note that the 4060 Ti is the successor to the 3050 Ti, not the 3060 Ti, as clarified by lndig0\_\_.

Infinity Cache and Power Draw

ResponsibleJudge3172 and whotheff explain that the lower bus width is likely due to cost savings and power draw control. To compensate, the memory clock is increased. This design choice is similar to AMD's RDNA2 architecture, which also utilizes Infinity Cache to improve performance.

In conclusion, while the series 40 cards have lower memory bus width than previous generations, it's not necessarily a bad thing. The improvements in GPU die, L2 cache, and memory clock frequency contribute to increased performance and memory bandwidth. As whotheff suggests, future generations may adopt finer chip processes, leading to higher bus widths and improved performance.

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